HiSilicon
(Image credit: HiSilicon)
New e-mails from Huawei engineers regarding Linux kernel development suggest that HiSilicon - Huawei's chip subsidiary - is prepping a new Kunpeng SoC with HBM (High Bandwidth Memory) technology - as highlighted by Phoronix. This will likely be the the first significant release from HiSilicon in a while but don't get your hopes up as it could also just be a rebranded older model with a slight pinch of HBM.
Kunpeng is a series of server SoCs from HiSilicon that were originally designed using Arm's Cortex cores. HiSilicon later transitioned to custom Arm-based Taishan cores with the Kunpeng 920 featuring 64 such Taishan V110 cores fabricated using TSMC's 7nm process. Plans for future versions were spoiled in light of US sanctions as China was and still is unable to procure bleeding-edge nodes from TSMC - with all Chinese chip makers reliant on SMIC. Just a few months back, a Kunpeng chip with Taishan V120 cores surfaced with performance similar to AMD's Zen 3 architecture so these processors do have something to show for themselves despite lackluster support on desktop.
A series of patches from Huawei has added support for an unnamed Kunpeng SoC featuring HBM in the Linux kernel. As far as public records go, HiSilicon never formally revealed any chip integrated with High Bandwidth Memory so this is indeed a new processor in the making. Nonetheless, the patches go over developing a driver for the Kunpeng SoC platform that offers the user an interface to power the HBM on or off depending on the workload.
"Add power control support for High Bandwidth Memory (HBM) for Kunpeng SoC platform. HBM devices on Kunpeng SoC can provide higher bandwidth at the cost of higher power consumption. Providing power control methods can help reducing the power when the workload does not need use HBM."
Linux Patches
HiSilicon is likely to stick with the Arm ISA but it might upgrade the aging Taishan design, up the core counts, and improve connectivity. As far as fabrication goes, SMIC's 7nm is the most probable candidate since nodes better than or equal to 5nm require special EUV machines. While it is theoretically possible to manufacture 5nm wafers without EUV - using techniques such as SAQC (Self-Aligned Quadruple Patterning) - the same method was the very reason Intel's 10nm node suffered delays and lost its competitiveness against TSMC.
Chinese chip makers have been barred from using Arm's advanced Neoverse V-series CPU cores for some time now. HiSilicon will likely leverage a modified version of the Armv8 ISA or even Armv9 for that matter since both architectures are not subject to the US trade ban. It will be interesting to see how these chips fare against the likes of Granite Rapids and Turin though we suspect a one-sided battle.
Hassam Nasir
Contributing Writer
Hassam Nasir is a die-hard hardware enthusiast with years of experience as a tech editor and writer, focusing on detailed CPU comparisons and general hardware news. When he’s not working, you’ll find him bending tubes for his ever-evolving custom water-loop gaming rig or benchmarking the latest CPUs and GPUs just for fun.