In a significant advancement for semiconductor technology, researchers at UC Santa Barbara have unveiled novel three-dimensional (3D) transistors utilizing two-dimensional (2D) semiconductors. Their approach paves the way for energy-efficient, high-performance electronics with unprecedented miniaturization potential.
“This breakthrough represents a major step toward the next generation of transistor technologies that can sustain the rapid progress of computing and artificial intelligence applications,” saidKaustav Banerjee,a professor of electrical and computer engineering and renowned expert in nanoelectronics and 2D materials. “By integrating atomically-thin 2D semiconductors into a 3D architecture, we have unlocked new possibilities for performance enhancement, transistor scalability and energy efficiency.”
Banerjee and his team’s work is published in thejournal Nature Electronics.
Pushing the limits of transistor miniaturization
To enhance the performance of existing devices and enable advancements in newer technologies, the strategy of choice has been to miniaturize transistors — the fundamental components of modern electronics — to pack them in more densely and enable more operations on the chip with the same die size.
Indeed, some of themost significant advances in miniaturizationhave resulted in the design and development of strained-silicon and high-k/metal-gate field-effect transistors (FETs) that addressed scaling challenges and enhanced performance. However, in the case of the mainstream silicon technology, the transistors could get only so small before they hit limits to their performance, particularly in the realm of energy efficiency. These limitations, known as “short-channel effects,” arose in the form of subthreshold leakage currents and poor switching, making it difficult to downsize these transistors while keeping power consumption low.
Many of these limitations were overcome with the introduction of the Fin-FET more than a decade ago, a type of 3D architecture that wraps a “gate” around the channel that runs from the transistor’s source to its drain, mitigating short-channel effects while allowing for a smaller footprint. However, according to the authors, the downscaling of transistors beyond 10 nm channel length while keeping the power consumption low with good-performance is increasingly challenging, even for state-of-the-art Fin-FETs.
In this regard, the UCSB team’s study reveals that the enhanced electrostatics of 3D gate-all-around (GAA) structured transistors, when implemented with 2D semiconductors, could be used to realize ultimately scaled, few-nanometer channel length transistors with significantly boosted performance and energy efficiency. They have abbreviated these 3D GAA transistors as NXFETs, where N=nano, and X=sheet, fork or plate represent the topology of the channel stacking. Their study establishes how such transistors can be uniquely engineered with 2D semiconductors.